Analysis on the integrity of the hottest power sup

2022-07-27
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Nowadays, power consumption has become the only major design constraint of integrated circuits, but power integrity has rarely attracted people's attention, although it plays an important role in determining power supply and energy consumption. Most people will notice that if the lights in the entertainment room are turned too dark, the sharp change in brightness on the TV screen will damage our eyesight. Therefore, the effect of reducing lighting energy consumption directly depends on the 'light noise' we encounter. The principle is exactly the same for IC. Minimizing energy consumption by reducing the supply voltage is the most basic method. This method directly depends on the power grid noise or power integrity. Power integrity is the next major challenge facing SOC and sip, as power and energy are still the dominant design constraints

power supply integrity concept

simply speaking, power supply integrity refers to the proximity of a specific power supply to an ideal state, which depends on the natural characteristics of the power supply. For the power supply of household equipment, the main concern is the voltage amplitude and frequency, that is, how stable the voltage amplitude and frequency can be regardless of the change of nearby load and power consumption limit. We may all notice that when the compressor of a large air conditioner or refrigerator starts, the light will dim, which is the deterioration of power integrity

what is the difference between integrated circuits? Although they generally use a few volts to one volt DC power supply. The power supply integrity of IC can be well understood by understanding the step-down and overshoot generated at this constant voltage when some circuits of IC are opened and closed, and functions are increased and decreased. For excellent power integrity, it is important that the step-down and overshoot or transient (and static) changes in the supply voltage difference remain within a small range, such as 5% of the nominal value, so that the integrated circuit can maintain predictable performance

the main components of supply voltage change in IC power supply grid are IR voltage drop and l × (di/dt), although other noise components sometimes dominate, such as propagation and reflection noise and resonance noise. At present, the analysis tools in EDA industry use IR voltage drop variation method to analyze the voltage drop of each part of integrated circuit. With the continuous reduction of process size, the relatively important power integrity noise components are also changing rapidly, mainly because most of the current integrated circuits function through binary operations containing circuit switching current and are synchronized with the clock signal. With the development of the process to the nanometer level, these switching speeds will increase rapidly, and the on-chip di/dt will be increased accordingly. Therefore, it is now necessary to check the 'overall power integrity', including L × (di/dt) and other electromagnetic effects, not just IR voltage drop or its derivative

loop inductance, l × (di/dt) and process influence

power supply integrity research shows that the loop inductance from the package capacitor to the processor needs to be changed to the 3rd to 5th power of the process change coefficient to maintain the same power supply integrity between the improved process and the previous generation process. In this example, the loop inductance determines the response delay from the package capacitance to the instantaneous charge required by the processor, and the corresponding voltage drop of the processor supply voltage

similarly, the on-chip loop inductance determines the response delay from the discharge of the charge stored in the chip or package area to the area requiring instantaneous charging, such as the function block of the fast switch or the register group, trigger or a large number of logic gates triggered by the clock at the same time. The loop inductance L and the current rise rate di/dt will also produce a voltage drop - L × (di/dt), this voltage drop will be superimposed on any instantaneous voltage drop caused by the neutral line resistance of the power distribution network. Therefore, it is necessary to judge how continuous process upgrading affects the L of the next generation of products through tests × (di/dt) voltage drop (noise). In order to complete this test, considering the process upgrading, benefits obtained and final results, the following assumptions are made according to the current industry trends:

· the capacitance CA per unit area, the adjustment ratio is about (1/0.7), of which 0.7 is the scaling factor caused by the typical manufacturing process (95nm to 65, 45, 32, etc.),

· the adjustment ratio of working voltage is 1/, the reduction is only about 16%,

· the frequency adjustment ratio is, There can be a 40% improvement

· the chip area adjustment ratio is 1/, which is only reduced by 30%, instead of 50%, indicating that another circuit is integrated to improve the performance of the scaled process

under the above assumption, the effective power can be obtained by referring to the "root of twice scaling", and the equation is assumed at this time α CV2 remains unchanged before and after process scaling. In this scaling case, the area of the silicon wafer is reduced, which reduces the cost, improves the frequency and integration, and increases the performance. At the same time, the power loss remains unchanged (assuming that there is a better leakage current control technology to keep the leakage power unchanged), so that the economic benefits still follow Moore's law

· under the above scaling conditions, the scaling factor of the average effective current is the reciprocal of the voltage scaling factor, that is, because the power remains unchanged

· since the frequency scaling factor is, the di/dt scaling factor is X

· in addition, since the chip area scaling factor is 1/, the scaling factor of each side (assuming a square chip) is 1/

if the size of each side is smaller, and assuming that the power bus is drawn with the same width and spacing, the number of parallel buses per side is reduced by 1/, or the effective inductance is increased

multiply L and di/dt in the chip after process scaling to obtain:

· L × (di/dt) the zoom factor is XX, or 2x

the above calculations are obviously highly simplified, and the scaling coefficient is also very inaccurate, but the trend is positive. With the evolution to finer process size, the switching edge rate will be faster and faster. In order to save effective power and leakage power, the devices will be smaller and smaller, and the operating voltage will be lower and lower. Although the power consumption may remain the same or even be expected to be reduced, faster processes require faster charge transfer or provide greater current through fewer available resources (such as metal power lines) and smaller capacitors, resulting in higher voltage drop

it can be seen from this simple derived formula that each process upgrade will make L × (di/dt) noise is doubled, which puts forward higher requirements for supporting elements. See reference [4] for details, although the power remains unchanged. E.g. L × (di/dt) or power supply network noise caused by induced noise is 9mv in 180nm process. According to the derived trend, the 45nm node will generate 16 times the induced noise, or about 144mv, which is about 15% of the differential value of the power supply, or 3 times the allowable maximum noise. Academic research also shows the same trend, that is, the induced noise increases to the power of two with the rise time, which depends on the PEEC modeling of the power distribution lattice. The IR voltage drop tool may completely miss this power integrity

chip or module designers will find that more advanced processes will increase the average supply current, and they must make difficult choices in power distribution grid design. Sometimes it is necessary to rely on the over hyped 'full copy' method. At this time, designers can allocate the same part of metal resources to the power distribution grid, just like the previous generation of chips (this can work, but must be done correctly!). As we previously deduced, the amount of instantaneous induced noise in the chip will double after scaling

next, the optimal IR voltage drop method in power integrity design and the influence of on-chip inductance on power integrity will be introduced in detail. In addition, it will also introduce in detail the problems that often exist in the integrity of power supply on newer process nodes such as 45nm, which lead to the decline of device yield, including the L × (di/dt) noise, serious lack of comprehensive power integrity technology and EDA tools, unable to clearly understand chip power integrity, etc. Finally, the possible solutions to these problems will be discussed

ir voltage drop and on-chip inductance

those designers who are more negative will follow the optimal IR voltage drop method and deduce that the average chip current will increase, so more power grid metal is required. Designers are faced with two options: one is to increase the number of power buses, which means reducing bus spacing; the other is to increase the width of metal wiring in the bus, but subject to the wiring requirements. Usually, designers will choose to increase the metal wiring width rather than reduce the bus spacing to make the wiring more crowded, and use the IR voltage drop tool to improve the noise. Unfortunately, this solution is not practical, especially when the main noise source is l × (di/dt), because increasing the metal wiring width and the axial isolation between buses has very limited effect on improving the noise, and even has a negative impact. In addition, the high-frequency current is usually limited to the low inductance region of the power bus

the above two flawed methods have a common factor, that is, they rely unusually on previous knowledge and experience, rather than relying on comprehensive verification to make up for the shortcomings of the methods. It can be predicted that this inappropriate dependence will certainly reduce the quality of work and even the final results. Just like financial investment with many uncertainties, past performance cannot guarantee future results. This industry inertia makes it impossible for people to turn to comprehensive power integrity analysis, mainly because of the serious lack of efficient and accurate modeling technology and EDA tools, so as to carry out fast, comprehensive and real electromagnetic simulation for IP modules, multi-core chips and the entire power system

in fact, academic research shows that the metal area of power supply can be better optimized by including induced noise in power grid simulation. In a paper on the influence of on-chip inductors on the design of power distribution network, it is written that the utilization rate of metal area in the power grid of 90nm process has increased or decreased by about 30%, and it can be improved by up to 60% through comprehensive on-chip power grid inductor modeling in 45nm process

outline drawing of triangular load current used for grid noise assessment

power supply integrity problem

methods such as quadratic or exponential growth or changing water level; L of × (di/dt) noise is a serious lack of comprehensive power integrity technology and EDA tools that can help IP cores and chip designers quickly simulate and analyze physical design, and can not clearly understand all aspects of chip power integrity. The design of operating procedures of soc2 and electronic tensile testing machine, for example, has irresistibly shifted to finer nanometer size. These factors together lead to the decline of device yield, Finally, the economic feasibility of process size reduction is reduced

superposition of power supply noise from two sources (line width 10 μ m. Spacing 50 μ m)

the variation of semiconductor devices using nano technology and the increasingly low operating voltage to reduce energy consumption further exacerbate the yield problem. Low power and low energy consumption design is not the same as no power integrity problems. In fact, on the contrary, low-power design will introduce additional complexity, such as power gating, which affects power integrity in a less explicit way. In order to achieve reasonable integration and performance, practical chips with operating voltage of only a few tenths of a volt need to deeply understand and comprehensively verify the narrow bandwidth noise allowed on their power supply. Another method is to convert all the determined area and efficiency digital logic circuits into

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